1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a semiconductor device including a power transistor.
2. Description of Related Art
For forming a high-power transistor, a plurality of MOS (Metal Oxide Semiconductor) transistors may be formed on a semiconductor substrate, and in these transistors, sources, drains, and others may be connected in common. Japanese Unexamined Patent Application Publication No. 2000-311953 describes such a power transistor with an exemplary use in an H bridge circuit. In Japanese Unexamined Patent Application Publication No. 2000-311953, the drawings all show the power transistor incorporated in the H bridge circuit, and thus for simplification of the drawing, FIGS. 15 to 17 show an exemplary case where the power transistor is a power MOSFET (Metal Oxide Semiconductor Field-Effect Transistor). By referring to FIGS. 15 to 17, described below is the configuration of such a power transistor.
FIG. 15 is a diagram showing the layout of a semiconductor substrate 100 with source regions 1, drain regions 3, and gate electrodes 2 formed thereon. Note here that FIG. 15 is not showing the semiconductor substrate and the semiconductor chip in their entirety but schematically showing a part of the layout in which a power transistor is disposed on the semiconductor substrate 100. As shown in FIG. 15, for forming a power transistor on the semiconductor substrate 100, a source region 1 (SOURCE), a gate electrode 2 (GATE), a drain region 3 (DRAIN), and a gate electrode 2 (GATE) are generally repeatedly disposed in this order, i.e., repeating structure. The source region 1 and the drain region 3 are each a diffusion layer formed on the semiconductor substrate 100, and the gate electrode 2 is a polysilicon line formed on the semiconductor substrate 100 with a gate oxide film (not shown) or the like interposed therebetween.
As shown in FIG. 15, the gate electrodes 2 are connected in common, and are electrically connected to a gate line (not shown) or the like. The source regions 1 are respectively connected, via contacts or the like, to underlying source lines 10 that will be described later by referring to FIGS. 16 and 17. The source regions 1 are also connected to a source pad 101 via an overlying source line 11. Similarly, the drain regions 3 are respectively connected to underlying drain lines 30, and are connected to a drain pad 102 via an overlying drain line 31.
By referring to FIGS. 16 and 17, described next is the wiring configuration of a typical power transistor. FIG. 16 is a top view of the power transistor, showing the underlying source lines 10, the underlying drain lines 30, the overlying source line 11, the overlying drain line 31, contacts 80 between the underlying and overlying source lines 10 and 11, and contacts 90 between the underlying and overlying drain lines 30 and 31. Note that FIG. 16 is not showing the source regions 1, the drain regions 3, and the contacts connecting these diffusion regions and the underlying lines. FIG. 17 is a schematic cross-sectional view of the power transistor of FIG. 16 taken along a line XVII-XVII.
As shown in FIG. 17, an interlayer insulation film 20 is formed on the semiconductor substrate 100. The source lines 10, and the drain lines 30 are formed on this interlayer insulation film 20. As shown in FIG. 16, the source lines 10 are substantially parallel to the source regions 1, and the drain lines 30 are substantially parallel to the drain regions 3. The source regions 1 and the drain regions 3 are connected to the source lines 10 and the drain lines 30 respectively by contacts 21.
A second interlayer insulation film 22 is formed over the underlying lines, i.e., the source lines 10 and the drain lines 30. The overlying lines, i.e., the source line 11 and the drain line 31 are formed on the second interlayer insulation film 22. As shown in FIG. 16, the overlying lines, i.e., the source line 11 and the drain line 31, are each formed from an extremely large and wide layer covering about a half of the area where the MOS transistors are formed. Such lines are hereinafter referred to as solidly-formed wiring layers. The overlying source line 11 is electrically connected to the source pad 101. The overlying drain line 31 is electrically connected to the drain pad 102. The contacts 80 are formed in the second interlayer insulation film 22 located below the overlying source line 11. With these contacts 80, the underlying source lines 10 are electrically connected to the overlying source line 11. The contacts 90 are formed in the second interlayer insulation film 22 located below the overlying drain line 31. With these contacts 90, the underlying drain lines 30 are electrically connected to the overlying drain line 31. FIG. 17 shows only the contacts 90 since it is the cross-sectional view of the portion where the overlying drain line 31 is formed. On the other hand, only the contacts 80 are formed below the portion where the overlying source line 11 is formed.
A semiconductor chip may have a plurality of power transistors. If this is the case, configuring a semiconductor chip forming a power transistor with the above-described two types of wiring layers, i.e., the overlying and underlying lines, will pose a difficulty. This thus results in a need for a semiconductor chip using a larger number of types of wiring layers.
In the resulting semiconductor chip, however, depending on the shape, size, and others of the wiring layers formed between the underlying lines and the overlying lines, i.e., uppermost solidly-formed wiring layers in the power transistor, we have now discovered that current concentration occurs in the underlying lines and the area in the vicinity of the pads in the power transistor, thereby possibly shortening the life of elements.
There thus has been a demand for preventing the increase of current density concentrated in a part of the lines with consideration given to the shape of such intermediate lines located between underlying lines and overlying lines connected to pads in a semiconductor device including a power transistor.